hi,
i got errors like this when running tb_eth_top module( in bench file )
.........pls help me............


# -- Compiling module tb_eth_top

# ** Error: C:/Documents and Settings/admin/Desktop/ethernet
/bench/verilog/tb_eth_top.v(1328): Undefined variable: Wrap.

# -- Compiling module tb_ethernet


thanks and regards,
surendra